About:

As the original disruptors in solid–state satcom–on–the–move antenna, my client is rewriting the book on phased arrays. It's one of the toughest challenges in satcom. And, so far, we are the only team to demo multi–axis capability in real world conditions.

Now we're closing in our goal: active electronically steered antennas (AESA) for super–fast, super–reliable connectivity–GEO, of course, but LEO, MEO and HEO too

Backed by USD 57 billion group mogul, we are attracting formidable partners: we have appointed a world–class, global manufacturing partner, and two of the world's best FABs are working on our chips.

Job Overview:

As a Principal RFIC Design Engineer/Head of ASIC design, you are responsible to lead the design of Ku/Ka band RF Transmitters & Receivers using deep sub–micron technologies for next generation of satellite communications. You are responsible for delivery of ASIC Specifications, architecture design, circuit design & verification, review, IC qualification & production release.

The job places you at the helm of ASIC development where you will develop new circuit architectures, design/verification methodologies to deliver ASICs that meet all the performance requirements in the required timeline. While the job primarily involves you to own and lead the chip–level development, you will work closely with the block–level design and layout engineers to conduct technical reviews and provide guidance and direction for successful delivery. You will also work closely with the test team in developing the test plan and characterising the ASIC.

Aside from leading a team of design engineers and mentoring them, you will work closely across the organisation from layout & test teams to systems, antenna, hardware teams to ensure on–time delivery of our ASICs that puts our Antennas at the leading edge of technology and well ahead of our competition.

You will report to VP–ASIC Engineering and assist in choosing the fabrication process & technology vendors, setup process flow and ensuring design governance, create product development plans and technology roadmaps.

Ideal candidate will typically have 10+ years of experience in the design of RFICs in deep submicron technologies with chip lead experience in 2 or more successful tape–outs.

Technical Responsibilities:

Responsible for ASIC specifications, architecture design, top level design & verification, block level designs and on–time tape–out of ASICs. Responsible for design of a transmitter & receiver blocks in Ku/Ka band in deep submicron CMOS technologies. Hands–on block–level design of various RF blocks such as PA, LNA, VGA, Phase shifters, Power Splitters/combiners Delivering high quality RF/Analog blocks with leading edge performance using innovative architectures and circuit implementations. Work closely with the layout team on IP floor–planning, trial layout design, parasitic extraction, and modifications.3 Co–ordinate and manage design activities with other colleagues and external technical contractors.

Qualifications & Skills:

An Engineering degree in a relevant discipline Minimum of 10 years' experience in RF, Analog and Mixed–Signal IC design (preferably 15GHz or higher operating frequencies) – including 2 or more successful tape–outs. Excellent demonstrated leadership skills to motivate and direct design teams to deliver. Excellent understanding of state–of–the–art RF CMOS circuit design and transceiver architectures Experience of designing high performance Analog/RF circuits in deep sub–micron technology as well as a strong analytical approach with a clear track record of success and delivery Cadence Virtuoso Design Framework Experience Ability to collaborate and co–ordinate work with engineering teams across multiple disciplines during ASIC project development.

If you are interested in learning more about this great offer, get in touch.